At the International Solid-State Circuits Conference (ISSCC) here, MIT claims that it has developed an ultra-low-power, 256-kilobit SRAM based on TI�s 65-nm process technology.
Using ultra-dynamic voltage scaling techniques � reportedly pioneered by MIT � the 0.4-volt, sub-threshold SRAM achieves 2.25 times lower leakage power, as compared to its six-transistor counterpart at 0.6 volts, according to TI and MIT. The SRAM also claims to incorporate 10 transistors per bitcell to enable operations down to 400-mV.
Ultra-dynamic voltage scaling is seen as a promising technology to reduce voltages at the sub-threshold level, said Dennis Buss, vice president of silicon technology development at TI (Dallas). The technology could enable ultra-low power devices at �the 45-nm node and beyond,� Buss said in an interview at ISSCC.
The collaboration between TI and MIT is partially funded by the Defense Advanced Research Projects Agency (DARPA). The development is part of an ongoing effort to create ultra-low power logic and memory devices for battery-operated products. "
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